Daniel Großmann M.Sc.

Contact

work +49-6151-16-20143
fax +49-6151-16-20582

Work S3|21 202
Fraunhoferstraße 4
64283 Darmstadt

Research project:

In modern power electronic inverters, fast-switching semiconductors are used. A typical structure is the half-bridge, a series of two transistors between a DC link, each with an anti-parallel (Schottky) diode and load tap in the middle (see figure – without red markings).

When the semiconductors are switched, the load current commutates to the opposite semiconductors, for example from the lower transistor to the upper diode. The load current itself changes only slightly due to the high load inductance. It continues flowing along the newly formed loop. All other hard-switched paths, the commutation circuit, experience an abrupt current change. Due to parasitic inductances, high induction voltages occur there, which are applied to the blocking semiconductors in addition to the DC link voltage. If the voltage rating is too low, the semiconductors may be destroyed. The following figure illustrates the drain-source voltage when the lower MOSFET is switched off, including the overvoltage due to the abrupt current change in the commutation circuit.

Parasitic inductances exist at many points in the commutation circuit: In the paths of the PCB from the DC link to the semiconductors, in the DC link capacitor itself (ESL), between the upper and lower semiconductors to the load tap, by current measurement in the commutation circuit, as well as in the connection pins of the semiconductors to the chip.

In addition other parasitic elements occur in the commutation circuit, such as resistances in the connection paths, capacitances between the paths on the PCB and also parasitic elements in the gate circuits, which also affect the switching behaviour of the transistors.

Particularly the capacitances in the semiconductors, which are suddenly charged and recharged when the half-bridge is switched and therefore significantly influence the commutation process, can lead to strong, unwanted oscillations (see figure below) in interaction with other parasitic elements in the commutation circuit. These are often ignored and damped by using snubber capacitors or avoided by increasing the gate resistance to reduce the switching rate and thus reduce the stimulation of the resonant circuit.

The goal of the research project is a detailed investigation of the effects during the commutation process of concentrated SiC-MOSFETS by laboratory measurements, the determination of the relevant factors and parasitic elements affecting the switching behaviour, an exact simulative reproduction and finally the optimization of the entire commutation cell.

For this purpose, the principle of the double pulse test is applied. The basic circuit is shown by the red additions in the first figure. The lower combination of MOSFET and Schottky diode forms the “device under test” (DUT), the variables shown are measured with high resolution and high bandwidth. Starting from a reference configuration, selected changes are made to the commutation cell and the gate circuits which are subsequently analyzed in order to identify the key design criteria for an optimal commutation cell.